The present invention relates to semiconductor processing, and more particularly to a method for minimizing nitride residue on a silicon wafer using a uniform oxide deposition followed by an optimized isolation oxide polish.
Transistor memory arrays are typically fabricated on a silicon wafer. The process usually begins by depositing a layer of pad oxide on the wafer substrate. Typically, the pad oxide is 150-250xc3x85 thick. A nitride mask is then deposited over the pad oxide and etched to define active regions on the silicon substrate. An isolation technology is then used to create isolation regions between the active regions to electrically isolate the active regions from one another. In shallow trench isolation (STI) for example, shallow trenches are etched into the silicon substrate in the openings in the nitride mask between the active regions. A liner oxidation process is then performed in the trenches in which a thin layer of oxide is grown. Next, an oxide such as TEOS (tetraethyl orthosilicate) or HDP (high-density plasma) is deposited over the silicon substrate and is then polished back so that it remains only in the trenches, its top surface level with the nitride mask. After the oxide is etched back, the nitride mask is stripped to expose the pad oxide. Thereafter, layers of polysilicon are patterned to define stacked gate structures and word lines for the semiconductor device.
Unfortunately, the conventional processes for depositing and polishing the oxide, and for removing the nitride from the wafer may result in the formation of faulty devices. The oxide is deposited on the wafer using a low-pressure chemical vapor deposition system (LPCVD) in which gasses continuously flow into a reaction chamber holding the wafer where deposition occurs. The LPCVD deposition, however, results in a non-uniform layer of oxide on the wafer due to an edge to center temperature gradient and depletion of reactive gasses in the chamber.
FIG. 1A is a top view of a silicon wafer 10 after oxide deposition with cross-sectional views showing the center area of the wafer 10 and the edge area of the wafer 10, respectively. The dotted lines in the top view are graphical representations of trench isolation areas 12 beneath the layer of isolation oxide 14, which is shown in the cross-sectional views deposited over the nitride mask 16 to fill the trenches 12. During oxide deposition, more of the oxide gas reacts on the surface of the wafer 10 along the edge area, while less of the oxide gas reaches the center area of the wafer 10, resulting in the oxide being approximately 100-200xc3x85 thicker in the edge area of the wafer 10 compared to the center area. This difference in oxide thickness is shown graphically by the arrows. For a 200 mm wafer, for example, the edge area of the wafer where the oxide becomes non-uniform may be 5-20 mm in size, while the center area may be 195-180 mm in size.
After the isolation oxide 14 is deposited, the oxide 14 is polished down to the top level of the nitride 16. Once goal of the polishing process is to cease polishing just before the nitride layer is encountered, which in the ideal case would leave a thin skin of oxide 14 above the nitride. The next step is to remove this thin skin of oxide 14 by way of an HF dip etch. Because of the non-uniformity in the thickness of the oxide 14, however, more oxide 14 will remain in the edge area of the wafer 10 than in the center after polishing, and the HF dip etch will fail to remove all of the oxide 14 in the edge area of the wafer 10.
After the dip etch, the nitride is stripped from the wafer 10 with a bath of hot phosphoric acid and, which does not attack oxide 14. FIG. 1B is a top view of the wafer 10 after the nitride strip. Because the acid does not affect the oxide 14, if there is any oxide 14 remaining on top of the nitride 16, the nitride 16 will not be removed under these areas, leaving nitride residue 18 in the edge area of the wafer 10. The problem with nitride residue 18 is that it will block formation of the subsequent transistor structures and cause defects in the memory array.
Accordingly what is needed is method for minimizing nitride residue on a silicon wafer. The present invention addresses such a need.
The present invention provides a method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer. The method further includes performing an optimized polishing process on the oxide wherein the oxide is polished down to approximately a level of the nitride, but where more of the oxide is removed from the edge area of the wafer than in the center area. Thereafter, the nitride is stripped from the wafer.
According to the present invention, because all of the oxide is removed, substantially all of the nitride can be removed from the wafer during the nitride strip, thereby minimizing nitride residue and increasing the reliability of the resulting semiconductor devices.